index - Equipe Secure and Safe Hardware Accéder directement au contenu

 

Dernières publications

Mots clés

Loop PUF Aging Differential Power Analysis DPA Application-specific VLSI designs Image processing FDSOI CPA Information leakage Linearity Fault injection attack Coq Intrusion detection Field programmable gate arrays Countermeasure Cryptography Variance-based Power Attack VPA MRAM Formal proof Fault injection Resistance Process variation Circuit faults Magnetic tunnel junction Machine learning Security services Formal methods Internet of Things Authentication Signal processing algorithms Side-Channel Analysis Voltage 3G mobile communication Field Programmable Gates Array FPGA Routing FPGA STT-MRAM Lightweight cryptography Costs Power-constant logic Hardware security Differential power analysis DPA Randomness Security Magnetic tunneling Robustness Logic gates Power demand Sensors AES Side-Channel Attacks Side-channel analysis Receivers DRAM Protocols Transistors Filtering Reverse-engineering Masking countermeasure SCA Switches Reverse engineering Security and privacy Spin transfer torque Asynchronous Tunneling magnetoresistance Side-channel attacks SCA Defect modeling Sécurité Countermeasures Hardware CRT RSA Random access memory Writing Simulation SoC OCaml Reliability Training Convolution Energy consumption Dual-rail with Precharge Logic DPL Side-Channel Analysis SCA Side-channel attacks Dynamic range Elliptic curve cryptography Neural networks Mutual Information Analysis MIA Temperature sensors GSM ASIC Masking TRNG Computational modeling PUF Estimation Side-channel attack Confusion coefficient Electromagnetic Steadiness

 

Documents avec texte intégral

213

Références bibliographiques

428

Open access

39 %

Collaborations